AN204 vishay siliconix document number: 70602 10-aug-99 www.vishay.com faxback 408-970-5600 6-1 serially-controlled 8-channel analog switch array simplifies signal conditioning and routing when analog signals are processed in a digital system, some of the processing must be performed in the analog domain, both before and after the digital portion of the system. cmos analog switches are frequently used in a variety of analog signal conditioning functions under digital control, such as gain ranging, anti-aliasing filter corner-frequency selection, sample-and-hold functions, input channel selection, input summing, and signal routing. a new serially-controlled array of precision cmos switches simplifies the design of these functions, while improving system accuracy and reducing component count and board space. this application note presents simplified solutions for some of these digitally controlled analog signal processing circuits using the new dg485 eight-channel serially-controlled switch array. the dg485 switch array cmos analog switches typically come in single, dual, and quad configurations. cmos multiplexers combine up to sixteen switches on a chip, with decoding logic that allows the selection of one switch at a time. now there is a new function that combines the best of both types of devices. the dg485 has eight switches on a chip, and through a unique serial data control architecture, any combination of the eight switches can be connected to a common output line. a new way to control a switch array the internal block diagram for the dg485 is shown in figure 1. it consists of five elements: (1) the logic input stages, (2) an array of eight d-type flip-flops that form an input shift register, (3) an array of eight data latches, (4) eight switch drivers, and (5) eight cmos analog switches. there are three power supply inputs and a ground. the three supplies are v+, v, and v l . v+ and v set the analog range for the signals being controlled by the switches. the range of operation for v+ and v is 5 v to 20 v and also includes single-supply operation by connecting v to ground. the v l input determines the logic switching threshold recognized by the logic input buffer stages. the nominal operating value for v l should be 5 v to allow for ttl-compatible operation (v inl 0.8, v inh 2.4 v). however, v l can be operated anywhere from 5 to 40 v to facilitate compatibility with a wide range of logic levels. the gnd, although being the only ground point on the device, is generally considered to be a digital ground, rather than an analog ground, for the purpose of avoiding ground loops. q clk d a z a clk dq d type latch driver switch q clk d a za clk dq d type latch driver switch q clk d a za clk dq d type latch driver switch z z z z a a a a clk ld ttl in v l d in rs r r r q q q z a a s 1 s 2 s 8 d out d figure 1. the dg485 internal block diagram z z a
AN204 vishay siliconix www.vishay.com faxback 408-970-5600 6-2 document number: 70602 10-aug-99 address register shift register type flip1 flop latch d- s d z v q d clk ld v+ data input gnd d clk clk (1) (2) (3) (4) (5) level-shift v l level-shift cmos switch z q rs rs figure 2. simplified schematic of a typical dg485 channel a simplified schematic of a typical dg485 channel which details its five elements is shown in figure 2. the input buffer stages (1) are cmos inverters which have esd protection consisting of catch diodes and a resistor to dissipate the energy generated by electrostatic discharge, which can destroy an mos input. the scheme used in the dg485 provides protection in excess of 4000 v on all pins of the device. (this protection is required only on the logic inputs because the power supply and output connections have built-in protection via the large parasitic p-n junctions.) the ttl input buffers are cmos inverter stages that swing between v l and gnd, and drive a level shift stage to drive the d-type master-slave flip flops (2) that swing from v+ to gnd. the d-type flip-flops have master-slave inverters with edge-sensitive clocking, and they form the data input shift register. their outputs are connected to the address register latches (3), which are single-stage clocked-inverter flip-flops with level-sensitive clocking. these latches, in turn, are connected to the switch drivers (4), which provide level translation from the latch outputs, which swing between v+ and gnd, to the gates of the cmos switches (5), which must swing from rail to rail. these switches are pairs of large p-channel mosfets in parallel with complementary n-channel mosfets; this parallel combination has a low on-resistance of 85 : (maximum at 25 c). the p-channel device is turned on by driving its gate to the v rail, and it is turned off by driving its gate to the v+ rail. in an opposite manner, the n-channel device is turned on by driving its gate to v+ and turned off by driving its gate to v. these parallel switches compensate for each other's increase in on-resistance as the analog signal approaches either rail. that is, as the v gs for one device goes to zero, it shuts off, while the opposite polarity device is fully enhanced or turned on hard. the result is a fairly flat on-resistance as the analog voltage of the source (or drain) ranges from v+ to v. typically, a 8 variation is seen. controlling the array with a serial data bus the dg485 connects to the serial output of a microprocessor system, as shown in figure 3. the eight cmos switches in the dg485 are controlled via the serial data output via the d in (data in) pin. data is loaded into the eight-bit shift register with each clock pulse at the clk (clock) input. the contents of the shift register are loaded into the octal latch when a logic ahigho signal is applied to the ld (load) input. the octal latch holds the state (on or off) of the individual switches in the array. the rs (reset) input resets the octal latch to all azeroeso when a logic alowo is applied, turning all switches off with a subsequent ld command. analog-signal voltage ranges the power supplies for the device are v+, v, and v l . the analog signal range of the switches is defined by the power supply rails. because the dg485 is built on a 44 v silicon-gate cmos process, rail-to-rail signal swings are possible. the power supply voltages range from 5 v to 20 v, and single-supply operation is allowed from +5 v to +40 v. the logic levels are set with v l input. with 5 v applied to v l , ttl and 5 v cmos logic compatibility (v inl = 0.8 v, v inh = 2.4 v) is assured.
AN204 vishay siliconix document number: 70602 10-aug-99 www.vishay.com faxback 408-970-5600 6-3 switch array octal latch shift register ld clk dg485 8085 ale r/s 8212 (8) (8) address bus decoder 8205 sod d +15 v 15 v +15 v v+ v gnd wr data bus rs d in d out to next switch array v l s 1 s 2 s 8 figure 3. the dg485 simplifies analog signal control with a serial data bus. the input shift register in the dg485 receives switch on/off-state data directly from the serial data (sod) line from the microprocessor. switch array with improved speed and accuracy in addition to being a useful new function, the dg485 features analog switches with vastly improved performance. they are part of the dg400 family which uses a new silicon-gate cmos process designed to achieve improved speed, lower power, lower on-resistance, lower leakage, and improved esd tolerance. these benefits are the result of the inherent reduced overlap parasitic capacitance of silicon-gate cmos processing. for comparison of switch performance, key specifications for the industry-standard dg508a eight-channel multiplexer and the dg485 eight-channel array are shown in table 1. the closest standard ic to the dg485 is the eight-channel dg508a multiplexer. while the dg485 array allows any combination of eight switches to be turned on at one time (compared with the one-of-eight decoding of the multiplexer), it also has improved speed and accuracy with reduced power dissipation. key specifications for the dg485 array and the dg508a multiplexer are compared in table 1. key specification (@ 25 c) dg508a 8-channel multiplexer dg485 8-channel array fabrication process 44 v metal-gate cmos 44 v silicon-gate cmos on-resistance (r ds(on) max.) 450 85 leakage (i s(off) max.) 5 na 1 na switching time (t (tran) max.) 1 s (1000 ns) 200 ns power dissipation (pd max.) 59 mw (59000 w) 105 w esd tolerance 500 v 4000 v
AN204 vishay siliconix www.vishay.com faxback 408-970-5600 6-4 document number: 70602 10-aug-99 + dg485 d + (a) (b) dg485 continuous v in v out s 1 s 2 s 3 s 8 s 1 s 2 s 3 s 8 figure 4. gain ranging and attenuator circuits digitally controlled signal conditioning input signal conditioning functions like gain ranging, programmable attenuation, and variable filter time constant circuits have one thing in common they use analog switches for selecting various resistor values. there are many ways to create digitally controlled gain stages using cmos switches. using the dg485, as shown in figure 4a, places the analog switch in series with a high-impedance point, such as the input of an op amp, to eliminate errors associated with switch on-resistance. additionally, the gain value is determined by the ratio of the gain-setting resistors rather than their absolute value. thus, the accuracy of the gain setting is a function of the matching or scaling of the resistors, independent of resistor or analog switch variations. if matched or monolithic resistor arrays are used, excellent gain accuracy and low gain drift is achieved with this architecture. the dg485 allows for selection of eight different resistor ratios under serial control, and its any-combination-of-eight architecture also allows 255 different parallel combinations of resistor ratios for additional gain ranges. a variation on this theme, shown in figure 4b, provides programmable attenuation. again, the analog switches are placed in series with a high-impedance point (the op amp input) to eliminate the effect of switch resistance variations. attenuation values are selected according to the ratio of the resistors in the string. digitally controlled filter the programmable filter circuit shown in figure 5 selects resistors rather than capacitors to change the rc time constant of the low pass. this is a useful function at the input of a data acquisition or digital signal processing system which allows the processor to adjust the corner frequency of its anti-aliasing filter if various sample rates are being used. only one capacitor is required, and resistors (which are generally low in cost and easier to specify for accuracy and ratios) are selected with the dg485 to generate different filter characteristics. resistors that are matched to the ones in the feedback loop are switched at the input of the integrator to maintain unity passband gain for any of the four corner frequencies selected. in this filter topology, unlike the gain-ranging circuit shown above, the analog switches are placed in series with the time-constant setting resistors. therefore, the resistance characteristics of the switches play a significant role in the accuracy of the time constant selection. switches with low on-resistance are preferred since the time constant of the filter is (r ds(on) + r f ) c. if r f is large, compared to the 85- on-resistance of the dg485, accurate filter break frequencies may be selected via digital serial control. r in is chosen according to the dc gain requirement of the system. for example, dc unity gain inversion is achieved with r in = r f . the break frequency, f 3db , is calculated as f 3db 1 2 rc the actual measured 3 db frequencies may vary as much as 10% due to the parasitic drain and source capacitance of the dg485 switches and the variation in on-resistance seen from channel to channel. because any combination of the eight switches can be selected, there are a total of sixteen different rc values that can be programmed by using parallel resistor combinations for a wide range of filter roll-offs.
+ c = 10,000 pf lf356 +15 v 15 v v in v out 0.1 mf r 1 s 5 r 2 s 6 r 3 s 7 r 4 s 8 r 1 s 1 r 2 s 2 r 3 s 3 r 4 s 4 f 3db = 1/(2prc) 0.1 mf figure 5. programmable low pass filter AN204 vishay siliconix document number: 70602 10-aug-99 www.vishay.com faxback 408-970-5600 6-5 code to shift register 1 2 3 4 5 6 7 8 f 3db r 1 = 1.6 k 1 0 0 0 1 0 0 0 10 khz r 2 = 800 0 1 0 0 0 1 0 0 20 khz r 3 = 530 0 0 1 0 0 0 1 0 30 khz r 4 = 400 0 0 0 1 0 0 0 1 40 khz dg485 + v +15 v 15 v d clk ld dg485 d clk ld load clock serial data in #1 #3 v out = (v 1 + v 2 + ... v n ) for r f = r in r f v out v 1 v 2 v 8 v 17 v 18 v 24 s 1 s 2 s 8 d out d in s 1 s 2 s 8 d out d in figure 6. the summing-node mixer is frequently used in audio production consoles. inputs are switched on and off with the summing node of the dg485. r in switching, selecting, and summing multiple inputs frequently a system will process signals from multiple inputs. time division multiplexing takes samples of each input in successive time intervals. the traditional approach is a multiplexer followed by a sample-and-hold circuit. the dg485 simplifies this function while allowing faster data throughput and higher precision. the channel selection is accomplished with a serial data line, eliminating the latches that are required with a multiplexer, such as the dg508a, when interfacing with the data bus. in addition, the sample-and-hold function is covered by the dg485 with a hold capacitor. the reduced on-resistance and faster transition time of the dg485 allows faster sample acquisition, and the low leakage reduces droop rate.
AN204 vishay siliconix www.vishay.com faxback 408-970-5600 6-6 document number: 70602 10-aug-99 the summing-node mixer an eight-channel summing amplifier processes eight inputs in a different way. like the time-division multiplexer, it selects eight inputs, but rather than sampling each input, it adds the inputs to one another. a classic example is the audio mixer, which sums many audio inputs at the summing node of an op amp to a single output (see figure 6). for precision, low-noise systems, it is important that the switch resistance remain low because the switches are placed directly in series with the summing resistors and, hence, the analog switches become a factor in the gain and nonlinearity (which results in distortion) of the system. the any-combination-of-eight function of the dg485 allows summing, where the conventional multiplexer function only allows selection of one at a time. in addition, the reduced on-resistance of the dg485 allows a factor of six reduction in the values of the summing resistors, thus reducing noise. the serial control line vastly simplifies addressing in larger mixers. a 24-channel mixer is easily configured without additional address lines using the d out (serial data output) feature of the dg485 to daisy-chain the switch arrays (see figure 6). the summing-node mixer is a variation of the basic inverting amplifier. if you consider only one channel of the circuit and assume r in and r f >> r ds(on) of the dg485 (85 ), then the transfer expression is v out = (r f /r in ) v in or v out + v in when r f = r in v out r f r in r ds(on) v in v out = (r f /r in ) v in or v out + v in when r f = r in if improved gain accuracy or low values of r f and r in are required, the effect of r ds(on ) cannot be ignored. the expression becomes v out r f r in r ds(on) v in placing a dummy aono switch from the dg485 into the feedback loop in series with r f will provide an r ds(on ) term in the numerator of the expression. v out (r f r ds(on) ) r in r ds(on) v in or for r f = r in v out = v in when all channels are included, super position gives v out = (v 1 + v 2 + ... v n ) for n inputs. crosspoint arrays an audio crosspoint array provides interconnection between many inputs and many outputs. the serial data addressing feature of the dg485 simplifies the control of a high-quality audio-frequency crosspoint array, such as the one shown in figure 7. this eight-input, four-output crosspoint uses four dg485s. cross connection is directly controlled by a 32-bit serial-control word by taking advantage of the dg485's serial-data output pin. by daisy-chaining the switch arrays, the control data is sent through an effective 32-bit shift register, the contents of which are latched into the 32-bit address register on a ld command which is common to all four dg485s. the clk and rs functions are also shared by all four chips. figure 7. an eight-byfour audio crosspoint serial data input dg485 dg485 dg485 dg485 clk ld clk ld clk ld clk ld load clk in 1 in 2 in 8 out 1 out 2 out 3 out 4 d out d in d out d in d out d in d in
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